Regular Extreme Fast Charging Station for E-buses with Low Current Harmonic Content

ABSTRACT

Public transport vehicles based on electric vehicles are suitable for regular extreme fast charging (R-XFC) with supercapacitors as energy storage. Quick recharges cause power quality problems such as high harmonic injection. In this sense, grid-connected converter solutions must address this issue. The main objective of this paper is to present a solution for R-XFC stations with the Zero Harmonic Distortion (ZHD) Converter. The ZHD converter features elements consolidated in the industry and it does not need capacitive filters in the point of common coupling (PCC) with the grid, presenting sinusoidal currents with low harmonic content for regular extreme fast charging (R-XFC) stations. Hardware-in-the- loop (HIL) simulation results of an extreme fast recharge showed a total demand distortion (TDD) of 0.54%, and experimental results of a 280 kVA prototype had a TDD of 2.29%.

KEYWORDS
extreme fast charging; vehicle charger; regular extreme fast recharge; electric vehicles; e-bus; TUPF; ZHD; energy storage

I. INTRODUCTION

An alternative structure for electric public transport is the regular extreme fast charging (R-XFC) station. Usually, public transport buses have pre-defined stops, which allow the installation of R-XFC stations in specific locations. Based on this, the authors at [¹] show the design of an electric minibus with hybrid storage of batteries and supercapacitors, with recharges providing autonomy of almost 1 km in 50 seconds. Since 2009, there have been bus projects in China with supercapacitors for extreme fast recharges that reach 5 to 8 km per recharge in a few minutes [²]. E-buses using up to 40 kWh supercapacitors can be found as a commercial alternative to compound an electric vehicle fleet [³].

Due to the high power of XFC stations, problems with the injection of harmonics into the grid are more evident. The high injection of harmonics into the grid caused by extreme fast recharge systems would be able to change the original resonance point of the Dutch transmission grid of Bronsbergen from 1600 Hz to 1250 Hz, reached by the characteristic harmonics of 12-pulse converters [⁴]. Resonances could generate overvoltages and overcurrents in the transmission line, damaging the electric system, and increasing losses. In [⁵], the authors show the impact of an ultra-fast charging station for electric buses. Some of the individual harmonic levels of the input current exceed the limits established by IEEE 519-2022 [⁶], mainly for low-order harmonics. These power quality issues are the subject of studies on prediction, modeling, and control for the mitigation of these harmonics [⁷], [⁸].

Thus, international standards and recommendations such as IEC 61000-3-6 [⁹] or IEEE-519-2022 define maximum limits for harmonic amplitudes in the electrical grid and limits for indices such as total harmonic distortion (THD) for voltage harmonics and total demand distortion (TDD) for current harmonics. In this context, a grid-connected converter that meets the harmonic injection standards is recommended.

For high-power applications such as R-XFC stations, the 12-pulse three-phase diode bridge can be used as a grid-connected converter. However, this solution has low power quality due to the high harmonic content of its current, requiring an ac filter and a bulky de filter, besides not allowing the control of the output voltage [¹⁰].

Topologies such as Neutral Point Clamped (NPC) converter, Vienna rectifier, and Swiss rectifier are also presented as alternatives but, in general, require LCL filters to reduce the harmonic content [¹¹]– [¹⁹]. When these topologies work at high frequency, problems such as high switching losses and electromagnetic interference arise. By reducing the frequency, the LCL passive filters connected to the grid become bulkier, create resonance points, and increase application costs [²⁰].

Topologies that do not require second-order filters are more attractive to avoid points of resonance in the grid. Using a substantial number of levels enables the elimination of a second-order ac filter [²¹]. The authors in [²²] use a 5-level E-type rectifier as a grid-connected converter in an ultra-fast charger for electric buses. However, even with a switching frequency of 20 kHz and a multilevel converter, the current THD reached 4.7%.

One solution that could be used in XFC stations is the Modular Multilevel Cascaded Converter (MMCC). It could be used in various applications for transportation electrification, such as rail interties, railway power conditioner, and propulsion systems [²⁴]- [²⁶]. However, galvanic isolation is necessary to protect consumers, avoiding electric shocks, in compliance with IEC 62955:2018 and IEC 61851-1:2017 regulations and IEEE Std 2030 [²⁷]– [²⁹], which requires the use of a transformer in MMCC solution, such as the solid-state transformer [¹⁸]. In addition, the MMCC has a high number of components, bringing additional reliability and control challenges.

Table 1 presents a comparison of various aspects of different papers with topologies and prototypes focusing on extreme fast charging stations. The performance of all mentioned systems is strongly dependent on the control scheme and parameters, as it is in the proposed system. The power quality metrics in XFC based on the converter proposed in this paper are achieved through proper modulation strategy and control implementation as discussed in the following sections. Therefore, an analysis of the control adequacy for the several mentioned systems is not within the scope of this paper.

TABLE 1
Comparison between proposed topologies for extreme fast charging stations.

Grid-connected converter	LC Filter?	Diodes/Switches	Switches Technology	fsw (kHz)	Sim. Power (kW)	Exp. Power (kW)	THDi (%)
Conventional 2-level [11]	✓	0/6	SiC	100	50	✗	4.04a
Conventional NPC [12]	✗	6/12	Si	1.08	240	1.2	2.46a/✗
NPC 4-leg [13]	✓	8/16	Si	2.16	1200	3.6	5.39a/5.8b
Conventional Vienna [14]	✗	6/6	Si	12/50	60	1.865	3.27a/3.5b
Vienna 3-sw. [11]	✓	18/3	SiC	100	50	✗	1.26a
Vienna 6-sw. [11]	✓	12/6	SiC	100	50	✗	1.26a
Parallel Vienna [15]	✗	12/6	Si	15	30	6.0	0.847a/7.11b
Swiss [17]	✓	8/8	SiC	90	✗	10	4.9b
5-level E-type [22]	✗	12/36	Si	20	✗	25	4.7b
MMCC [26]	✓	120/120	Si	1.0	600	✗	1.25a
Proposal: ZHD converter	✗	0/18	Si	1.14	280	280	0.54a/2.29b

• ^a
  Simulation results.
• ^b
  Experimental results.

Figure 1 illustrates the Zero Harmonic Distortion (ZHD) converter, which serves as an alternative to XFC stations. Introduced in [³⁰], the ZHD converter is designed with a minimal component count and utilizes industry-standard elements. It also operates at a low switching frequency (1.14 kHz for 2-level converter), which is crucial for minimizing losses in converters that use high-power Si switches. Notably, it does not require capacitive filters at the point of common coupling (PCC), ensuring sinusoidal currents with low harmonic distortion. This design eliminates harmonics up to the 50th order, aligning with the IEEE 519-2022 recommendation [⁶].

FIGURE 1
Zero Harmonic Distortion converter.

The topology consists of a three-winding transformer with a 30-degree angular phase shift between the secondary windings, which cancels harmonics of the order 6n ± 1 It includes input reactors to attenuate the amplitude of harmonics present in the secondary windings and employs two- or three-level converters that utilize 9-pulse selective harmonic elimination pulse width modulation (SHE PWM) combined with dq-axis current control. The 9-pulse SHE PWM effectively eliminates harmonics of the order 12n ± 1.

Table 2 summarizes the key publications on the ZHD converter, previously referred to as the True Unity Power Factor (TUPF) converter. Despite advancements in ZHD current control and full-scale experimental validation, its application as a grid-connected converter for vehicular applications remains limited. The study by [²⁰], which precedes this work, explores the use of the ZHD converter for regular extreme fast charging of electric buses. However, it does not address the control of the ZHD for this application nor provide details on the control of the DC-DC converter.

TABLE 2
Main publications of ZHD converter (formerly True Unit Power Factor - TUPF).

Reference	Main area	Application	ZHD voltage control?	DC-DC converter control?	ZHD closed-loop experimental results?	Prototype power
[30]a	Power systems	Not specified	✗	-	✗	No data
[20]	Vehicular	Electric charger	✗	✗	✗	No data
[31]	Mining industry	Electric drive system	✓	-	✗	No data
[32]	Power systems	Wind system	✓	-	✗	30 kW
[33]	Metal industry	Electric drive system	✓	-	✓	30 kW
[34]	Metal industry	Static compensator	✓	-	✓	280 kW
[35]	Metal industry	Not specified	✓	-	✓	280 kW
[36]	Power systems	Islanded microgrids	✗	-	✓	4 kW
[37]	Power systems	Islanded microgrids	✓	-	✗	-
This paper	Vehicular	Electric charger	✓	✓	✓	280 kW

• ^a
  First study of the ZHD converter, still named TUPF.

The main contribution of this paper is to address the gaps in [²⁰] by providing detailed information on the voltage and current controllers of the ZHD converter and the DC-DC converter, the design of the e-bus capacitor bank, and presenting hardware-in-the-loop simulations along with experimental results using a full-scale prototype of the ZHD converter. This paper also presents the power losses and efficiency of the ZHD converter prototype.

This paper is divided into six sections: after the Introduction, section II presents the characteristics of the selective harmonic elimination pulse width modulation (SHE PWM). Section III discusses the control design of the converters present in the R-XFC station. Sections IV and V present the hardware-in-the-loop and experimental results, respectively, and the conclusions are presented in Section VI.

II. SELECTIVE HARMONIC ELIMINATION

The SHE PWM used in the ZHD converter was initially proposed in [³⁸] and improved in [³⁹]. It consists of modifying the switching angles of the switches throughout the operation cycle, to eliminate harmonics up to M − 1, where M is the number of switching state changes per half-cycle. The calculation of the switching angles depends on the number of converter levels, the number of harmonics to be eliminated, and the modulation index. It can be expressed in Fourier Series as shown in (1), which needs to be solved to meet a desired modulation index (m_i) while eliminating the chosen harmonics. Figure 2 presents a generic 2-level SHE PWM waveform.

$$\left[\begin{array}{c}1-2cos\left({\alpha }_1\right)+\cdots +2{\left(-1\right)}^M•cos\left({\alpha }_M\right)\\ 1-2cos\left(n_2•{\alpha }_1\right)+\cdots +2{\left(-1\right)}^M•cos\left(n_2•{\alpha }_M\right)\\ ⋮\\ 1-2cos\left(n_i•{\alpha }_1\right)+\cdots +2{\left(-1\right)}^M•cos\left(n_i•{\alpha }_M\right)\end{array}\right]=\left[\begin{array}{c}{m}_i\\ 0\\ ⋮\\ 0\end{array}\right]$$ (1)

To find the solution for (1) it is necessary to use numerical methods, such as Newton's linear iteration method [³⁰], [³⁸] using the partial derivatives of $\overrightarrow{f}$ to improve the initial guess of the angles and find a solution.

FIGURE 2
A generic 2-level SHE PWM waveform.

Switching angles are calculated offline using Newton's method, defined based on modulation indices, and stored in Lookup Tables (LUTs). SHE modulation needs high data processing to provide high-resolution switching angles. In this way, the ZHD control is subdivided into two parts, as shown in Fig. 4. DC bus voltage and grid current control loops are stored in a Digital Signal Processor (DSP). A Field-Programmable Gate Array (FPGA) performs the SHE PWM with superior processing based on the modulation rates sent by the DSP. The communication between the DSP and the FPGA is parallel, ensuring a high data exchange rate between the devices.

III. CONTROL DESIGN

Fig. 3 shows the schematic of the proposed solution for the R-XFC station using the ZHD converter emulated in the real-time simulation environment. Subsections A and B presents the ZHD converter control design and 3-arm interleaved DC/DC converter control design.

FIGURE 3
Proposed solution for extreme fast charger using ZHD.

A. ZHD control design

Fig. 4 shows the ZHD control. The current controller is composed of feedback control strategies, feed-forward command, axis decoupling, and a combination of the open-loop system with an estimate of the plant parameters. Based on the dynamic stiffness [⁴⁰], the gains of the current controller are calculated so that the poles of the system are spaced in a decade and keep the SHE PWM technique working satisfactorily [³³]. The expression for dynamic stiffness is presented in (2).

$$\frac{V^{dq}\left(s\right)}{I^{dq}\left(s\right)}=sL+K_p^{dq}+\frac{K_i^{dq}}{s}$$ (2)

The voltage controller sends the active power reference to the current controller. The controller chosen was the classic PI, combined with feed-forward strategies to anticipate disturbances in the current drained from the DC link and variations in the voltage reference.

The de link voltage disturbance is the current drain. This current drained from the de link has high-frequency components that impact the cascade current control. According to [³³], the commands to the modulator must be slower than the frequency on the rotary axis dq of the first non-eliminating harmonics (720 Hz). Therefore, set the moving average filter dynamics at 50 Hz, at least a decade below the modulator. Equation (3) represents the mathematical model of the dynamic stiffness curve of the system for controller tuning.

$$\frac{I_{dc}\left(s\right)}{V_{dc}\left(s\right)}=s{C}_{eq}+k_{pv}+\frac{k_{iv}}{s}$$ (3)

Figure 5 presents the curves of dynamic stiffness for the ZHD converter current loop control and voltage loop control. Equations (4) and (5) present the tuning for current controller and voltage controller, respectively. Table 3 shows the controller gains.

$$K_{pdq}={\omega }_{2i}L\text{and}{K}_{idq}={\omega }_{1i}{K}_{pdq}$$ (4)

$$K_{pv}={\omega }_{2v}C\text{and}{K}_{iv}={\omega }_{1v}{K}_{pv}$$ (5)

FIGURE 4
Schematic of controller in dq coordinates for the converters connected to the Δ and Y bridges.

FIGURE 5
Dynamic stiffness curves for ZHD converter: (a) Current control. (b) Voltage control.

TABLE 3
ZHD Converter controllers adjust.

Parameter	Controller Values
	Current Controller		Voltage Controller
	d-axis	q-axis
Poles Frequency	72 Hz	{72, 7.2} Hz	{7.2, 0.72} Hz
Proportional Gains	0.18 Ω	0.18 Ω	0.5 S
Integral Gains	-	8.15 Ω· s-1	2.2 S· s-1

B. 3-arm interleaved DC/DC converter control design

The dc/dc interleaved converter performs the interface between the dc link and the e-bus supercapacitor bank due to its simplicity, high current capacity, and reduced output current ripple [⁴¹]. Furthermore, non-isolated converters have greater efficiency than isolated converters [¹⁸] and galvanic isolation is guaranteed by the transformer present in the ZHD converter.

Fig. 6 presents the 3-arm interleaved dc/dc converter controller. It is important to emphasize that the current controller must be individual per converter arm. The reference of the current control loops of each arm comes from the output of the voltage controller. This output, in turn, is limited by a saturator with the maximum current value for the application. Such approach, performed in [⁴²] for supercapacitor recharging, allows a simple Constant Current - Constant Voltage (CC-CV) charge control [⁴³]. In addition, feed-forward actions anticipate supercapacitors' voltage disturbances and reference current variations.

Dynamic stiffness of the current controller, expressed by (6), defines the integral (K_iib) and proportional (K_pib) gains of the current controller. For current control, the disturbance is the variation of the voltage of the supercapacitor bank (V_Cap), and the output is the current in the inductor (I_L) according to (6). L_dc represents the inductance of the dc/dc converter.

$$\frac{V_{Cap}\left(s\right)}{I_L\left(s\right)}=s{L}_{dc}+K_{pib}+\frac{K_{iib}}{s}$$ (6)

The desired voltage for e-bus recharge defines the voltage controller reference of the dc/dc converter. The controller is composed of a classic PI with anti-windup due to the saturation of the controller output. Feed-forward strategies are used to anticipate variations in the reference voltage.

The dynamic stiffness of the voltage controller, shown in (7), defines the proportional (K_pvb) and integral (K_ivb) gains. For the presented system, the disturbance is the discharge current (I_Load) for the e-bus electrical and electronic systems. C_eq is the equivalent capacitor formed by the e-bus capacitor bank.

$$\frac{I_{Load}\left(s\right)}{V_{Cap}\left(s\right)}=s{C}_{eq}+K_{pvb}+\frac{K_{ivb}}{s}$$ (7)

Figure 7 presents the curves of dynamic stiffness for the 3-arm interleaved converter current loop control and voltage loop control. Equations (8) and (9) present the tuning for current controller and voltage controller, respectively. Table 4 shows the controller gains.

$$K_{pib}={\omega }_{2ib}{L}_{dc}\text{and}{K}_{iib}={\omega }_{1ib}{K}_{pib}$$ (8)

$$K_{pvb}={\omega }_{2vb}C\text{and}{K}_{ivb}={\omega }_{1vb}{K}_{pvb}$$ (9)

FIGURE 6
Schematic of the 3-arm interleaved dc/dc converter controller.

FIGURE 7
Dynamic stiffness curves for 3-arm interleaved converter: (a) Current control. (b) Voltage control.

TABLE 4
3-arm interleaved converter controllers adjust.

Parameter	Controller Values
	Current Controller	Voltage Controller
Poles Frequency	{500 Hz, 50 Hz}	{5, 0.5} Hz
Proportional Gains	1.88 Ω	3040 S
Integral Gains	592 Ω· s-1	9551 S· s-1

IV. HIL RESULTS

Table 5 shows the parameters of the ZHD converter based on a laboratory prototype. Table 5 also shows the main parameters of the dc/dc converter used in the extreme fast charger. The supercapacitor bank was designed based on AVX manufacturer SSC LE Series ultracapacitor [⁴⁵]. Considering the manufacturer's recommendation of the maximum excursion of 50% of the voltage in the supercapacitor, a 3.37 kWh bank was designed, as shown in Table 6.

TABLE 5
ZHD converter and 3-arm interleaved dc/dc converter parameters.

ZHD Converter
Element	Parameter	Value
Grid	Voltage [V]	440
	Frequency [Hz]	60
Transformer	Nominal power [kVA]	305
	Primary voltage [V]	506
	Secundaries voltage [V]	440
	Connection	Dd0y1
ac reactors	Δ/Y inductance [μH]	590/506.8
dc link	Capacitance [mF]	10.5
	dc link voltage [V]	700
DC/DC Converter
Parameter	Symbol	Value
Input voltage	Vi	700 V
Switching frequency	fsw	5 kHz
Max power	Pcharger	308 kW
Output voltage	Vo	250 to 500 V
Output current	Io	570 A
Output current ripple	ΔIo	3%
dc inductance per arm	Ldc	600 μH

TABLE 6
Capacitive cell and ultracapacitor bank characteristics.

Cell voltage	2.7 V
Cell capacitance	500 F
Cell series resistance	1.6 mΩ
Strings in parallel/series	36/186
Initial and final bank voltage	250-500 V
Bank capacitance (Ceq)	97 F
Bank series resistance	8.3 mΩ

In the 3-arm interleaved dc/dc converter, the difference between reactors was introduced to compensate for the leakage inductance difference between transformer windings. Three half-bridge arms with carriers shifted by 120° compose the 3-arm interleaved dc/dc converter. The current in the inductor of each arm is three times lower than the output current of the supercapacitor bank. Equation (10) defines the inductance per arm, where N is the number of arms, f_sw is the switching frequency, V_in is the input voltage, and V_o and ΔI_o are the output voltage and current ripple, respectively.

$$L_{dc}=\frac{V_o-V_o^2/V_{in}}{\Delta I_o.N.f_{sw}}$$ (10)

Fig. 8 shows the Typhoon Hardware-in-the-loop (HIL) 604 test bench. A TMS320F28335 DSP [⁴⁶] performs the 3-arm interleaved dc/dc converter control. Another TMS320F28335 DSP performs the control of the ZHD converter in a communication with a MAX 10 FPGA [⁴⁷], which performs the SHE PWM and PLL algorithm at a sufficiently fast sample frequency (250 kHz). The modulation index and the space vector angle are encoded in unsigned 10 bits and signed 13 bits, respectively, and sent simultaneously over a 23-bit parallel channel from the FPGA to the DSP. There is no traditional communication protocol between the DSP and the FPGA, only a 23-bit parallel synchronous communication with a 2.58 kHz clock.

The PLL algorithm has a significant influence on the control performance of converters connected to grids increasingly disturbed by the presence of nonlinear loads and sources, which has driven extensive research aimed at proposing increasingly robust and reliable PLLs [⁴⁸]. In this paper, the Double Decoupled Synchronous Reference Frame PLL (DDSRF-PLL) was chosen, as it is capable of accurately tracking the positive sequence angle in unbalanced grids and demonstrated good performance even in highly distorted electric grids [⁴⁹].

FIGURE 8
HIL bench for extreme fast charger implementation.

Fig. 9 shows the dc link voltage of the ZHD converter and the supercapacitor voltage and current during the 46 second charging period. The current in the supercapacitor remains constant during most of the charging period until it reaches zero when the voltage across the capacitor reaches 500 V. It is also possible to highlight the automatic change from the constant current mode to the constant voltage mode near the end of the recharge.

FIGURE 9
ZHD dc link voltage (CH1), supercapacitor current (CH2) and voltage (CH3).

Fig. 10 shows the currents in the supercapacitor and arms of the dc/dc converter. The ripple in the supercapacitor current is 24 A, three times less than the ripple in each converter arm (72 A). Fig. 11 shows the voltage and currents on the grid during supercapacitor recharge.

FIGURE 10
A-arm current (CH1), B-arm current (CH2), C-arm current (CH3) of dc/dc converter and supercapacitor current (CH4).

FIGURE 11
Grid voltage (CH1) and currents in phase A (CH2), phase B (CH3) and phase C (CH4) during supercapacitor recharging.

Fig. 12 shows a sinusoidal aspect of the currents in the grid due to the low harmonic content. There are no significant harmonics in the current phase A of the grid. Total demand distortion has a value of 0.54%.

FIGURE 12
Harmonic content of the current in phase A of the grid.

V. ZHD EXPERIMENTAL RESULTS

A. Half Power Tests

In order to experimentally validate the grid side portion of the proposed solution, the 280 kVA 2-level Zero Harmonic Distortion converter of Fig. 13 was used. The IGBTs used in 2-level converters are the FS450R12KE3 model from Infineon. Fig. 14 shows the scheme of back-to-back test. The back-to-back test allows the converter to be submitted to full power without a load, using the grid to supply only the system losses and, therefore, saving energy during the tests.

FIGURE 13
ZHD converter prototype.

FIGURE 14
Back-to-back test scheme.

For half power tests, the substation selector switch is connected to position 1, supplying the converter with 220 V. Figure 15 presents a dynamic ramp current variation test on the grid. The ramp was applied with a variation of 1173 A/s, ranging from 0 to 352 A in 300 ms. It can be observed that there is no current overshoot, and the system behaves smoothly. Figure 16 shows, in steady state, the voltage V_ABand the current in phase A of the transformer primary, in addition to the currents in the A phases of the secondaries in Δ and Y.

FIGURE 15
Ramp test: Grid Voltage V_AB(CH1) and line currents of the transformer primary (CH2, CH3 and CH4).

FIGURE 16
Half Power Test (steady state): Grid Voltage V_AB(CH1) and line currents of the transformer primary (CH2, CH3 and CH4).

B. Full Power Tests

For full power tests, the substation selector switch is connected to position 2. The substation transformer 2 (ST2) impedance is 8.88 + j20.3 mΩ (X/R = 2.3 and SCR = 29.12), characterizing a strong grid. It is also worth noting that the power of the substation transformer is nearly the same as that of the prototype transformer. The use of non-linear loads, like a diode rectifier, close to the rated power of the electric grid increases its voltage distortion, as shown in Fig. 17. It is worth noting that the rectifier diode is not part of the ZHD converter.

Fig. 17 shows the voltage V_AB and the current in phase A in the transformer primary, in addition to the currents in the A phases of the secondaries in Δ and Y. The phase difference between the line voltage and line current is 30 degrees, as expected. Due to distortions caused by the rectifier diodes in the back-to-back test, the primary voltage has a distorted appearance. The currents in the secondaries are distorted due to the presence of harmonics of order 6n ± 1.

FIGURE 17
Grid Voltage V_AB(CH1) and phase A current of the transformer primary (CH2), in the secondary in Δ (CH3) and in the secondary in Y of the transformer (CH4).

Despite the harmonic distortion of the grid voltage caused by the back-to-back test, the primary current has a sinusoidal aspect, corroborated by Fig. 18, which shows the harmonic content of the grid current. There is no harmonic content above the limits established by IEEE 519.

Fig. 18 also shows that the ZHD converter maintains low harmonic content in the grid current, even under adverse conditions of grid voltage distortion. The current total demand distortion (TDD) was 2.29%, below the IEEE 519 limit. Therefore, the ZHD converter is an alternative that does not overload the power grid with massive harmonic injection. Moreover, due to the lack of ac bulky filter, it does not create resonance points in the grid.

FIGURE 18
(a) Current in the transformer primary. (b) Harmonic content of the current in the transformer primary.

C. Power Losses

Figure 19 shows the setup for measuring power losses in the ZHD converter prototype. The Yokogawa WT1800 power analyzer was used to measure losses in each component.

FIGURE 19
Setup for measuring power losses.

Figure 20 shows the connection diagram used to measure power losses in the prototype, including the diode bridges. A similar diagram was realized to measure power losses in the transformer and reactors individually.

FIGURE 20
Diagram connection for measuring total power losses.

Since there is no accessible connection point to separate the power losses in the diode bridges, DC link, and 2-level converters, the input current in the diode bridges was measured, and power losses were calculated based on the diode datasheet. The power losses in the 2-level converters were calculated using the IGBT datasheet, phase current, and gate driver commands. DC link power losses were calculated as the difference between the total power loss and the losses in the other components. Table 7 presents the power losses in each element of the ZHD converter prototype. The inverter operation is expected to produce more losses than the rectifier one, since losses in the freewheeling diodes are less than in the IGBTs.

TABLE 7
Loss distribution in full-scale prototype (Load at 86.4% of nominal active power).

Conversion	Power Losses		Efficiency
Stage	[W]	[%]	[%]
Diode bridges	922	7.77	99.63
DC linka	2730.61	23.02	98.90
IGBTs converters	1836.00	15.48	99.25
Reactors	3070	25.89	98.74
Transformer	3301.39	27.84	98.62
TOTAL	11,860	100	95.23
ZHD converter (w/o diode bridges)	10,938	92.23	95.58
ZHD converter (w/o DC link)	8,207	69.21	96.65

• ^a Includes the DC link inductors, capacitors and resistors.

Figure 21 presents the simulated efficiency curve based on the prototype's component parameters. The efficiency calculation does not account for losses in the DC link, as obtaining its parameters—such as the capacitor type, DC inductors, and other components—was not feasible. From the analysis of the curve, it is observed that the ZHD with the transformer consistently achieves an efficiency above 96%, except at 10% load power. Meanwhile, the complete charger maintains an efficiency close to 95% across nearly the entire load range. The most significant losses occur in the transformer and reactor, primarily due to ohmic losses.

FIGURE 21
Efficiency by load.

VI. CONCLUSIONS

With the insertion of XFC in the power system, power quality is an important issue. The topologies that can be used in XFC have low power quality, lots of components, complex control, or do not comply with international standards and recommendations. In this context, the Zero Harmonic Distortion converter is a solution to meet power quality requirements according to international standards, using ordinary components and simple control.

Zero Harmonic Distortion converter showed grid current total demand distortion results of of 0.54% obtained in hardware-in-the-loop results and 2.29% in experimental results, below the limits established by IEEE 519, even in highly distorted grids.

Thus, the extreme fast charger based on the Zero Harmonic Distortion converter proved to be a viable solution to meet the various standards and recommendations. Supercapacitors are an interesting strategy, but the topology can also be used with batteries that support high-power recharges.

ACKNOWLEDGMENT

The authors would like to thank the support from Brazilian agencies CNPQ, CAPES and Minas Gerais state agency Fapemig.

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Edited by

• Associate Editor
  Levy F. Costa https://orcid.org/0000-0001-7372-8041

• Editor-in-Chief
  Heverton A. Pereira https://orcid.org/0000-0003-0710-7815

Publication Dates

• Publication in this collection
  11 Aug 2025
• Date of issue
  2025

History

• Received
  13 Nov 2024
• Accepted
  04 Apr 2025
• Published
  16 Apr 2025